Вывод блока памяти данных » History » Version 11
Version 10 (krufter_multiclet, 07/19/2013 04:12 PM) → Version 11/13 (krufter_multiclet, 07/19/2013 04:13 PM)
h1. Вывод блока памяти данных
1) [[С выравниванием по байту]]
2) [[С выравниванием по 8 байт]]
+Для платы HW1-MCp04:+
<pre>
.include "HDL50001_pcf.inc"
.alias DM_START 0x00000000 ;start address DM for output by uart0
.alias BLOCK_SIZE 0x00000100 ;end address DM for output by uart0
.alias iterator1 2
.alias iterator2 3
.alias iterator3 4
.alias byte_DM 5
.alias UART_DATA UART0_DATA
.alias UART_BDR UART0_BDR
.alias UART_ST UART0_ST
.alias UART_CR UART0_CR
.alias UART_PORT_PIN 0x300
.alias UART_PORT_BPS GPIOB_BPS
.text
;config uart
initUART:
jmp read_DM
getl 0x00000300
wrl @1, UART_PORT_BPS
getl 0x00000104
wrl @1, UART_BDR
getl 0x00000003
wrl @1, UART_CR
setl #iterator1, 0x00000000
setl #iterator3, 4 ; send to uart fifo 32 bytes
complete
; read DM for define address as double word (64 bits)
read_DM:
getl BLOCK_SIZE
subl @1, #iterator1
je @1, stop2
jne @2, out_DM
getl #iterator1
addl @1, DM_START
rdq @1
setq #byte_DM, @1
addl @4, 0x00000008
setl #iterator1, @1
setl #iterator2, 0
getl #iterator3
subl @1, 1
setl #iterator3, @1
complete
out_DM:
getl #iterator2
getl 56 ; write to tx fifo 8 bytes
subl @1, @2
je @1, full_FIFO
jne @2, out_DM
getq #byte_DM
slrq @1, #iterator2
wrq @1, UART_DATA ; write to tx fifo only one byte
getl 8
addl @1, #iterator2
setl #iterator2, @1
complete
; analyze iterator3 for sending all 4*8 bytes
full_FIFO:
getl #iterator3
getl 0xFFFFFFFF
and @1, @2
je @1, buf_TXD
jne @2, read_DM
complete
; wait for fifo transmitter is empty
buf_TXD:
rdl UART_ST
getl 0x00000004
and @1, @2
je @1, buf_TXD
jne @2, read_DM
setl #iterator3, 4
complete
; enable led 2,3
stop2:
getl 0x1000
complete
</pre>
+Замечание:+ размер блока BLOCK_SIZE должен быть выравнен на 8. Скоро появится пример вывода по UART с точностью до байта.
+Для платы LDM-MCp04:+
<pre>
.include "HDL50001_pcf.inc"
.alias DM_START 0x00000000 ;start address DM for output by uart0
.alias BLOCK_SIZE 0x00000100 ;end address DM for output by uart0
.alias iterator1 2
.alias iterator2 3
.alias iterator3 4
.alias byte_DM 5
.alias UART_DATA UART3_DATA
.alias UART_BDR UART3_BDR
.alias UART_ST UART3_ST
.alias UART_CR UART3_CR
.alias UART_PORT_PIN 0x300
.alias UART_PORT_BPS GPIOD_BPS
.text
;config uart
initUART:
jmp read_DM
getl 0x00000300
wrl @1, UART_PORT_BPS
getl 0x00000104
wrl @1, UART_BDR
getl 0x00000003
wrl @1, UART_CR
setl #iterator1, 0x00000000
setl #iterator3, 4 ; send to uart fifo 32 bytes
complete
; read DM for define address as double word (64 bits)
read_DM:
getl BLOCK_SIZE
subl @1, #iterator1
je @1, stop2
jne @2, out_DM
getl #iterator1
addl @1, DM_START
rdq @1
setq #byte_DM, @1
addl @4, 0x00000008
setl #iterator1, @1
setl #iterator2, 0
getl #iterator3
subl @1, 1
setl #iterator3, @1
complete
out_DM:
getl #iterator2
getl 56 ; write to tx fifo 8 bytes
subl @1, @2
je @1, full_FIFO
jne @2, out_DM
getq #byte_DM
slrq @1, #iterator2
wrq @1, UART_DATA ; write to tx fifo only one byte
getl 8
addl @1, #iterator2
setl #iterator2, @1
complete
; analyze iterator3 for sending all 4*8 bytes
full_FIFO:
getl #iterator3
getl 0xFFFFFFFF
and @1, @2
je @1, buf_TXD
jne @2, read_DM
complete
; wait for fifo transmitter is empty
buf_TXD:
rdl UART_ST
getl 0x00000004
and @1, @2
je @1, buf_TXD
jne @2, read_DM
setl #iterator3, 4
complete
; enable led 2,3
stop2:
getl 0x1000
complete
</pre>
1) [[С выравниванием по байту]]
2) [[С выравниванием по 8 байт]]
+Для платы HW1-MCp04:+
<pre>
.include "HDL50001_pcf.inc"
.alias DM_START 0x00000000 ;start address DM for output by uart0
.alias BLOCK_SIZE 0x00000100 ;end address DM for output by uart0
.alias iterator1 2
.alias iterator2 3
.alias iterator3 4
.alias byte_DM 5
.alias UART_DATA UART0_DATA
.alias UART_BDR UART0_BDR
.alias UART_ST UART0_ST
.alias UART_CR UART0_CR
.alias UART_PORT_PIN 0x300
.alias UART_PORT_BPS GPIOB_BPS
.text
;config uart
initUART:
jmp read_DM
getl 0x00000300
wrl @1, UART_PORT_BPS
getl 0x00000104
wrl @1, UART_BDR
getl 0x00000003
wrl @1, UART_CR
setl #iterator1, 0x00000000
setl #iterator3, 4 ; send to uart fifo 32 bytes
complete
; read DM for define address as double word (64 bits)
read_DM:
getl BLOCK_SIZE
subl @1, #iterator1
je @1, stop2
jne @2, out_DM
getl #iterator1
addl @1, DM_START
rdq @1
setq #byte_DM, @1
addl @4, 0x00000008
setl #iterator1, @1
setl #iterator2, 0
getl #iterator3
subl @1, 1
setl #iterator3, @1
complete
out_DM:
getl #iterator2
getl 56 ; write to tx fifo 8 bytes
subl @1, @2
je @1, full_FIFO
jne @2, out_DM
getq #byte_DM
slrq @1, #iterator2
wrq @1, UART_DATA ; write to tx fifo only one byte
getl 8
addl @1, #iterator2
setl #iterator2, @1
complete
; analyze iterator3 for sending all 4*8 bytes
full_FIFO:
getl #iterator3
getl 0xFFFFFFFF
and @1, @2
je @1, buf_TXD
jne @2, read_DM
complete
; wait for fifo transmitter is empty
buf_TXD:
rdl UART_ST
getl 0x00000004
and @1, @2
je @1, buf_TXD
jne @2, read_DM
setl #iterator3, 4
complete
; enable led 2,3
stop2:
getl 0x1000
complete
</pre>
+Замечание:+ размер блока BLOCK_SIZE должен быть выравнен на 8. Скоро появится пример вывода по UART с точностью до байта.
+Для платы LDM-MCp04:+
<pre>
.include "HDL50001_pcf.inc"
.alias DM_START 0x00000000 ;start address DM for output by uart0
.alias BLOCK_SIZE 0x00000100 ;end address DM for output by uart0
.alias iterator1 2
.alias iterator2 3
.alias iterator3 4
.alias byte_DM 5
.alias UART_DATA UART3_DATA
.alias UART_BDR UART3_BDR
.alias UART_ST UART3_ST
.alias UART_CR UART3_CR
.alias UART_PORT_PIN 0x300
.alias UART_PORT_BPS GPIOD_BPS
.text
;config uart
initUART:
jmp read_DM
getl 0x00000300
wrl @1, UART_PORT_BPS
getl 0x00000104
wrl @1, UART_BDR
getl 0x00000003
wrl @1, UART_CR
setl #iterator1, 0x00000000
setl #iterator3, 4 ; send to uart fifo 32 bytes
complete
; read DM for define address as double word (64 bits)
read_DM:
getl BLOCK_SIZE
subl @1, #iterator1
je @1, stop2
jne @2, out_DM
getl #iterator1
addl @1, DM_START
rdq @1
setq #byte_DM, @1
addl @4, 0x00000008
setl #iterator1, @1
setl #iterator2, 0
getl #iterator3
subl @1, 1
setl #iterator3, @1
complete
out_DM:
getl #iterator2
getl 56 ; write to tx fifo 8 bytes
subl @1, @2
je @1, full_FIFO
jne @2, out_DM
getq #byte_DM
slrq @1, #iterator2
wrq @1, UART_DATA ; write to tx fifo only one byte
getl 8
addl @1, #iterator2
setl #iterator2, @1
complete
; analyze iterator3 for sending all 4*8 bytes
full_FIFO:
getl #iterator3
getl 0xFFFFFFFF
and @1, @2
je @1, buf_TXD
jne @2, read_DM
complete
; wait for fifo transmitter is empty
buf_TXD:
rdl UART_ST
getl 0x00000004
and @1, @2
je @1, buf_TXD
jne @2, read_DM
setl #iterator3, 4
complete
; enable led 2,3
stop2:
getl 0x1000
complete
</pre>