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С выравниванием по 8 байт » History » Version 1

krufter_multiclet, 07/19/2013 04:12 PM

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h1. С выравниванием по 8 байт
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+Для платы HW1-MCp04:+
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<pre>
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.include "HDL50001_pcf.inc" 
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.alias DM_START		0x00000000 ;start address DM for output by uart0
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.alias BLOCK_SIZE	0x00000100 ;end address DM for output by uart0
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.alias iterator1 2
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.alias iterator2 3
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.alias iterator3 4
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.alias byte_DM 5
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.alias UART_DATA    UART0_DATA
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.alias UART_BDR     UART0_BDR
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.alias UART_ST      UART0_ST
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.alias UART_CR      UART0_CR
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.alias UART_PORT_PIN  0x300
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.alias UART_PORT_BPS  GPIOB_BPS
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.text
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;config uart
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initUART:
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    jmp read_DM
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    getl 0x00000300
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    wrl @1, UART_PORT_BPS
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    getl 0x00000104
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    wrl @1, UART_BDR
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    getl 0x00000003
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    wrl @1, UART_CR
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    setl #iterator1, 0x00000000
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    setl #iterator3, 4 ; send to uart fifo 32 bytes
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complete
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; read DM for define address as double word (64 bits)
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read_DM:
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    getl BLOCK_SIZE
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    subl @1, #iterator1
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    je @1, stop2
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    jne @2, out_DM
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    getl #iterator1
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    addl @1, DM_START
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    rdq @1
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    setq #byte_DM, @1
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    addl @4, 0x00000008
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    setl #iterator1, @1
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    setl #iterator2, 0
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    getl #iterator3
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    subl @1, 1
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    setl #iterator3, @1
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complete
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out_DM:
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    getl #iterator2
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    getl 56 ; write to tx fifo 8 bytes
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    subl @1, @2
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    je @1, full_FIFO
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    jne @2, out_DM
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    getq #byte_DM
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    slrq @1, #iterator2 
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    wrq @1, UART_DATA ; write to tx fifo only one byte
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    getl 8 
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    addl @1, #iterator2
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    setl #iterator2, @1
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complete
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; analyze iterator3 for sending all 4*8 bytes
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full_FIFO:
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    getl #iterator3
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    getl 0xFFFFFFFF
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    and @1, @2
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    je @1, buf_TXD
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    jne @2, read_DM
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complete
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; wait for fifo transmitter is empty
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buf_TXD:
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    rdl UART_ST
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    getl 0x00000004
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    and @1, @2
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    je @1, buf_TXD
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    jne @2, read_DM
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    setl #iterator3, 4
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complete
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; enable led 2,3
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stop2:
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    getl 0x1000
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complete
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</pre>
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+Замечание:+ размер блока BLOCK_SIZE должен быть выравнен на 8. Скоро появится пример вывода по UART с точностью до байта. 
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+Для платы LDM-MCp04:+
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<pre>
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.include "HDL50001_pcf.inc" 
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.alias DM_START		0x00000000 ;start address DM for output by uart0
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.alias BLOCK_SIZE	0x00000100 ;end address DM for output by uart0
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.alias iterator1 2
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.alias iterator2 3
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.alias iterator3 4
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.alias byte_DM 5
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.alias UART_DATA    UART3_DATA
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.alias UART_BDR     UART3_BDR
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.alias UART_ST      UART3_ST
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.alias UART_CR      UART3_CR
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.alias UART_PORT_PIN  0x300
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.alias UART_PORT_BPS  GPIOD_BPS
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.text
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;config uart
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initUART:
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    jmp read_DM
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    getl 0x00000300
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    wrl @1, UART_PORT_BPS
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    getl 0x00000104
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    wrl @1, UART_BDR
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    getl 0x00000003
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    wrl @1, UART_CR
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    setl #iterator1, 0x00000000
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    setl #iterator3, 4 ; send to uart fifo 32 bytes
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complete
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; read DM for define address as double word (64 bits)
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read_DM:
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    getl BLOCK_SIZE
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    subl @1, #iterator1
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    je @1, stop2
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    jne @2, out_DM
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    getl #iterator1
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    addl @1, DM_START
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    rdq @1
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    setq #byte_DM, @1
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    addl @4, 0x00000008
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    setl #iterator1, @1
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    setl #iterator2, 0
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    getl #iterator3
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    subl @1, 1
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    setl #iterator3, @1
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complete
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out_DM:
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    getl #iterator2
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    getl 56 ; write to tx fifo 8 bytes
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    subl @1, @2
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    je @1, full_FIFO
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    jne @2, out_DM
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    getq #byte_DM
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    slrq @1, #iterator2 
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    wrq @1, UART_DATA ; write to tx fifo only one byte
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    getl 8 
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    addl @1, #iterator2
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    setl #iterator2, @1
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complete
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; analyze iterator3 for sending all 4*8 bytes
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full_FIFO:
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    getl #iterator3
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    getl 0xFFFFFFFF
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    and @1, @2
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    je @1, buf_TXD
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    jne @2, read_DM
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complete
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; wait for fifo transmitter is empty
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buf_TXD:
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    rdl UART_ST
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    getl 0x00000004
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    and @1, @2
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    je @1, buf_TXD
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    jne @2, read_DM
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    setl #iterator3, 4
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complete
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; enable led 2,3
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stop2:
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    getl 0x1000
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complete
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</pre>