Eng multiclet R1 » History » Version 2
Version 1 (krufter_multiclet, 05/12/2015 02:02 PM) → Version 2/3 (krufter_multiclet, 05/12/2015 02:04 PM)
h1. Eng multiclet R1
Processor release date: December, 2014 year
*Sections:*
1) [[Eng_R1_assembl|Project build]]
*The Interfaces:* Periphery:
1) [[Eng_R1_PLL|PLL and clock]]
2) [[Eng_R1_GPIO|GPIO]]
3) [[Eng_R1_UART|UART]]
4) [[Eng_R1_I2C|I2C]]
5) [[Eng_R1_SPI|SPI]]
6) [[Eng_R1_DTC|DTC]]
7) [[Eng_R1_Ethernet|Ethernet]]
8) [[Eng_R1_USB|USB]]
9) [[Eng_R1_DAC|DAC]]
10) [[Eng_R1_I2S|I2S]]
11) [[Eng_R1_PWM|PWM]]
12) [[Eng_R1_MEMCTRL|Memory controller]]
*Additionally:* Additionally:
1) [[Eng_R1_AC|About architecture]]
Processor release date: December, 2014 year
*Sections:*
1) [[Eng_R1_assembl|Project build]]
*The Interfaces:* Periphery:
1) [[Eng_R1_PLL|PLL and clock]]
2) [[Eng_R1_GPIO|GPIO]]
3) [[Eng_R1_UART|UART]]
4) [[Eng_R1_I2C|I2C]]
5) [[Eng_R1_SPI|SPI]]
6) [[Eng_R1_DTC|DTC]]
7) [[Eng_R1_Ethernet|Ethernet]]
8) [[Eng_R1_USB|USB]]
9) [[Eng_R1_DAC|DAC]]
10) [[Eng_R1_I2S|I2S]]
11) [[Eng_R1_PWM|PWM]]
12) [[Eng_R1_MEMCTRL|Memory controller]]
*Additionally:* Additionally:
1) [[Eng_R1_AC|About architecture]]